describe

ADS5296A is a low-power, 12 bit, 8-channel, analog to digital converter (ADC) with a sampling rate of up to 80MSPS. However, this device can also be configured to operate as a 4-channel ADC, running at twice the sampling rate by interleaving the data of two ADC channels. In interleaving mode, the device accepts a double frequency input clock. ADC in each pair converts a common analog input signal on the alternate rising edge of twice the input clock. This device can be configured as a 10 bit, 4-channel ADC with a sampling rate up to 200MSPS, or a 12 bit, 4-channel ADC with a sampling rate up to 160MSPS.

The data of each ADC in the interleaved pair is output in serial format on an LVDS pair with a maximum data rate of 1Gbps (10 bits on 100MSPS). When interleaving is disabled, ADS5296A can operate as an 8-channel, 10 bit device with a sampling rate up to 100MSPS. Several digital functions commonly used in the system are also included in the device. These features include a Low Frequency Noise Suppression (LFNS) mode, digital filtering options, and programmable mapping of LVDS output pins to analog input channels.

For low input frequency applications, LFNS mode can realize noise suppression in low frequency state and improve the signal to noise ratio (SNR) in 1MHz band near DC by about 3dB. Digital filtering options include low pass, high pass, and bandpass digital filters, as well as DC offset cancellation filters. Low power consumption and multi-channel integration in a small package make this device an ideal choice for high channel number data acquisition systems. The device is packaged in a compact 9mm x 9mm QFN-64 package. The ADS5296A rated operating temperature range is - 40 ° C to+85 ° C.

characteristic

• Configurable operation mode:

– 10 bit, 200MSPS, 4-channel analog-to-digital converter (ADC)

– 12 bit, 160MSPS, 4-channel ADC

– 10 bit, 100MSPS, 8-channel ADC

– 12 bit, 80MSPS, 8-channel ADC

• Designed for low power consumption:

– 65mW per channel at 80MSPS (12 bit, 8 channels)

– 150mW per channel at 200MSPS (10 bit, 4 channels)

• 12 bit, 80MSPS:

– Signal to noise ratio (SNR): 70.3dBFS

• 10 bit, 200MSPS:

– Signal to noise ratio (SNR): 61.3dBFS

– Staggered spurious signal: greater than 60dB at 90MHz

• Serial low-voltage differential signaling (LVDS) single wire interface:

– Up to 10x serialization of 1000Mbps data rate per wire

– 12 times serialization of up to 960Mbps data rate per wire

• Digital processing block:

– Programmable Finite Impulse Response (FIR) decimation filter and oversampling to greatly reduce harmonic interference

– Programmable Infinite Impulse Response (IIR) high pass filter to minimize DC offset

– Programmable digital gain: 0dB to 12dB

• Low frequency noise suppression mode

• Programmable mapping between ADC input channel and LVDS output pin

• Channel equalization mode

• Multiple LVDS test modes to verify

Data capture of field programmable gate array (FPGA) or receiver

• Package: 9mm x 9mm square flat leadless (QFN) - 64 package

Scope of application

• Ultrasonic imaging

• Communication applications

• Multi channel data acquisition