Introduction
The TPS54618-Q1 device is a full-featured 6-Vin, 6-A, synchronous step-down current-mode DC-DC
converter with two integrated metal-oxide-semiconductor field-effect transistors (MOSFETs). The
TPS54618-Q1 device can operate in a wide range of switching frequencies from 200-KHz to 2-MHz. The
switching frequency can be set using a pulldown resistor or an externally applied signal at the RT pin as
shown in Figure 1. Refer to Interfacing TPS57xxx-Q1,TPS65320-Q1 Family, and TPS65321-Q1 Devices
With Low Impendence External Clock Drivers (SLVA755), for more information regarding interfacing an
external clock to TPS54618-Q1 family of devices.
The regulated output voltage at no load is given by Equation 1:
Vout = Vin × tON × fSW
where
•
Vin = input voltage
•
Vout = output voltage
•
tON = ON time
and
•
fSW = switching frequency
(1)
For given input and output voltages, as switching frequency is increased, tON will reduce. If tON falls below
the minimum value allowed by the internal circuit design, the output voltage may not track the internal 0.8-
V reference and would therefore not be regulated. To maintain the regulation at higher switching
frequencies, tON must be kept above a minimum value. If the switching frequency is less than or equal to
the data sheet maximum value of 2 MHz, tON will always be above designed minimum value and the
output would be regulated.
2
2.35-MHz Operation
Bench test and chip-level simulations were done to check whether the TPS54618-Q1 can remain in
regulation while switching at a frequency higher than 2.0 MHz.
The test conditions for the bench test and chip-level simulation were as follows:
•
Supply input voltage: 5.33 V
•
Regulated output voltage: 1.35 V
•
Operating switching frequency in bench setup: 2.35 MHz synchronized to an external clock as shown
in Figure 1.
Under these test conditions, the on time at a 100-mA load for the TPS54618-Q1 to maintain regulation
was verified by bench measurements to be 109.6 ns, compared to the value estimated by Equation 2:
(1.35 V / 5.33 V) × (1 / 2.35 MHz) = 107.8 ns
(2)
Minimum controllable on time at higher frequency and input voltage is verified to be less than 90 ns,
confirmed by the simulations in Section 3.
3
2.5-MHz Operation Simulation Results
A full chip breaking-point simulation is performed at 2.5-MHz clock frequency using the input and output
voltages specified in the following list to determine the minimum controllable tON allowed by internal circuit
design. The 2.5-MHz clock frequency is chosen to have some margin for oscillator tolerances and to be
sure that it works for 2.35-MHz clock frequency.
•
Input voltage swept from 5 V to 6 V
•
Output voltage programmed to 1.35 V
•
Load current set to 10 mA using a 135-Ω resistor
•
LOUT = 0.33 µH, COUT = 33 µF
•
RCOMP = 3.83 kΩ, CZERO = 1.5 nF, CPOLE = 0 pF
Simulation results:
•
Transient turn on behavior appears normal
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