describe

Xilinx introduces the programmable configuration prom in the system. These proms have a density of 1 to 32MB, providing an easy-to-use, cost-effective and reprogrammable method for storing large XilinxFPGA configuration bit streams. The platform flash Prom series includes 3.3vxcfxxsprom and 1.8vxcfxxpprom. The xcfxxs version includes 4MB, 2MB, and 1MB FPGAs that support the master serial and slave serial FPGA configuration modes (Figure 1, page 2). The xcfxxp version includes 32MB, 16MB and 8MB proms, which support master serial, slave serial, master select map and slave select mapfpga configuration modes (Figure 2, page 2).

When driven from a stable external clock, the prom can output data at a rate of up to 33MHz.

Table 1 lists the platform flashprom family members and supported features. 

features

• in system programmable Prom Xilinx for configuration ® FPGA

• low power advanced CMOS nor flash process

• durability of 20000 programming / erasing cycles

• operation over the entire industrial temperature range (– 40 ° C to +85 ° C)

• IEEE standard 1149.1/1532 boundary scan (JTAG) supports programming, prototyping, and testing

• JTAG command start configuration for standard FPGAs

• cascaded storage of longer or more bitstreams

• dedicated boundary scan (JTAG) input / output power supply (vccj)

• input / output pins are compatible with the following voltage levels 1.8V to 3.3V

• use Xilinx ISE ® Alliance and foundation ™ software package

•XCF01S/XCF02S/XCF04S

• 3.3V supply voltage

• serial FPGA configuration interface

• small size vo20 and vog20 optional packaging

•XCF08P/XCF16P/XCF32P

• 1.8V supply voltage

• serial or parallel FPGA configuration interface

• small vog48, fs48 and fsg48 packages

• design revision technical support storage and

Multiple design revisions accessed

to configure

• Xilinx compatible built-in data decompressor

Advanced compression technology