Xa7a35t-1cpg236q programmable logic device (CPLD / FPGA) is original and in stock
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Shenzhen nanbeihang Electronic Development Co., Ltd
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describe
Xilinx ® XAArtix ®- 7 (Automotive) FPGA is optimized for the lowest cost and power with small shape packaging for high-capacity automotive applications. With Sparta ®- Compared with the 6 series, designers can use more logic per watt.
Based on the most advanced high performance / low power consumption (HPL) 28nm high-k metal gate (HKMG) process technology, xaartix-7fpgas redefines more low-cost alternatives with logic per watt. Through 52gb / Si / O bandwidth, 100000 logical unit capacity, 264gmac / SDSP and flexible built-in DDR3 memory interface, the system performance is unprecedentedly improved, making a new class of high-throughput and low-cost automotive applications possible.
Xaartix-7 FPGA also provides many high-end functions, such as integrated advanced analog mixed signal (AMS) technology. Through the seamless realization of independent dual 12 bit, 1msps, 17 channel analog-to-digital converter, the analog system becomes the next level of integration. Most importantly, xaartix-7fpgas is proud to meet the high standards of automotive grade, with a maximum temperature of 125 ° C.
Characteristics
• vehicle temperature:
• class I: TJ = – 40 ° C to + 100 ° C
• class Q: TJ = – 40 ° C to + 125 ° C
• automotive standards:
• comply with ISO-TS16949 standard
• aec-q100 qualification
• production part approval process (PPAP) documents
• beyond aec-q100 qualification is available upon request
• advanced high-performance FPGA logic based on real 6-input look-up table (LUT) technology configurable as distributed memory
• 36 KB dual port block RAM with built-in FIFO logic for on-chip data
buffer
• sub watt performance of 100000 logical units
• High Performance Options ™ Technology supporting DDR3
Interface up to 800 MB / S
• high speed serial connection with built-in serial transceiver
500 MB / s with a maximum rate of 6.25 GB / s and a peak rate of 50 GB / s
Bandwidth (full duplex)
• a user configurable analog interface (xadc) with dual
12 bit 1msps analog-to-digital converter with on-chip thermal and
Supply sensor.
• single ended and differential I / O standards for speeds up to
1.25 Gb/s
• 240 dsp48e1 chips with up to 264 GMAC signal processing functions
• powerful clock management block (CMT) combined with phase locking
Loop (PLL) and mixed mode clock manager (MMCM) modules are used for high performance
Accuracy and low jitter
• for PCI Express ® (PCIe ®) Integrated block for up to X4 Gen2
End
• multiple configuration options, including
Memory with 256 bit encryption, hma-sha
Authentication, and built-in SEU detection and correction
• low cost wire bonding package for easy in
Family members in the same package, all packages are lead-free
• designed for 28 nm high performance and minimum power consumption,
HKMG, HPL process, 1.0V core voltage process technology
• a strong third-party ecosystem dedicated to automobiles with intellectual property rights,
Development Committee and design services