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Original DIP Programming IC Chips 256K OTP EPROM AT27C256R-15PC

256K (32K x 8) OTP EPROM AT27C256R-15PC

Features

• Fast Read Access Time - 45 ns

• Low-Power CMOS Operation – 100 µA max. Standby – 20 mA max. Active at 5 MHz

• JEDEC Standard Packages – 28-Lead 600-mil PDIP – 32-Lead PLCC – 28-Lead TSOP and SOIC

• 5V ± 10% Supply

• High Reliability CMOS Technology – 2,000V ESD Protection – 200 mA Latchup Immunity • Rapid™ Programming Algorithm - 100 µs/byte (typical)

• CMOS and TTL Compatible Inputs and Outputs

• Integrated Product Identification Code

• Commercial, Industrial and Automotive Temperature Ranges

Description

The AT27C256R is a low-power, high-performance 262,144-bit one-time programmable read only memory (OTP EPROM) organized 32K by 8 bits. It requires only one 5V power supply in normal read mode operation. Any byte can be accessed in less than 45 ns, eliminating the need for speed reducing WAIT states on high-performance microprocessor systems. Atmel’s scaled CMOS technology provides low-active power consumption, and fast programming. Power consumption is typically only 8 mA in Active Mode and less than 10 µA in Standby.

The AT27C256R is available in a choice of industry standard JEDEC-approved one time programmable (OTP) plastic DIP, PLCC, SOIC, and TSOP packages. All devices feature two-line control (CE, OE) to give designers the flexibility to prevent bus contention. With 32K byte storage capability, the AT27C256R allows firmware to be stored reliably and to be accessed by the system without the delays of mass storage media. Atmel’s 27C256R has additional features to ensure high quality and efficient production use. The Rapid™ Programming Algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 100 µs/byte. The Integrated Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry standard programming equipment to select the proper programming algorithms and voltages.

System Considerations

Switching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may exceed data sheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the VCC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again connected between the VCC and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array.