BY25D40ASTIG(T)
BY25D40/20
4/2M BIT SPI NOR FLASH
Memory Series
Features
● Serial Peripheral Interface (SPI)
- Standard SPI: SCLK, /CS, SI, SO, /WP
- Dual SPI: SCLK, /CS, IO0, IO1, /WP
● Read
- Normal Read (Serial): 55MHz clock rate
- Fast Read (Serial): 108MHz clock rate
- Dual Read: 108MHz clock rate SOP8 150-mil
● Program
- Serial-input Page Program up to 256bytes
● Erase
- Block erase (64/32 KB)
- Sector erase (4 KB)
- Chip erase
● Program/Erase Speed
- Page Program time: 0.7ms typical
- Sector Erase time: 100ms typical
- Block Erase time: 0.3/0.5s typical
- Chip Erase time: 3/2s typical SOP8 208-mil
● Flexible Architecture
- Sector of 4K-byte
- Block of 32/64K-byte
● Low Power Consumption
- 20mA maximum active current
- 5uA maximum power down current
● Software/Hardware Write Protection
- Enable/Disable protection with WP Pin
- Write protect all/portion of memory via software
- Top or Bottom, Sector or Block selection
● Single Supply Voltage
- Full voltage range: 2.7~3.6V USON8 3*2 mm
● Temperature Range
- Commercial (0℃ to +70℃)
- Industrial (-40℃ to +85℃)
● Cycling Endurance/Data Retention
- Typical 100k Program-Erase cycles on any sector
- Typical 20-year data retention at +55℃
1. Description
The BY25D40/20 is 4M/2M-bit Serial Peripheral Interface (SPI) Flash memory, and supports the
Dual SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO). The Dual Output data is
transferred with speed of 108Mbits/s. The device uses a single low voltage power supply, ranging
from 2.7 Volt to 3.6 Volt.
Additionally, the device supports JEDEC standard manufacturer and device ID.
In order to meet environmental requirements, Boya Microelectronics offers an 8-pin SOP 150-mil,
or 208mil, an 8-pin TSSOP 173-mil, an 8-pad USON 3x2-mm, and other special order packages,
please contacts Boya Microelectronics for ordering information.
Figure 1. Logic diagram
2. Signal Description
During all operations, VCC must be held stable and within the specified valid range: VCC(min) to
VCC(max).
All of the input and output signals must be held High or Low (according to voltages of VIH, VOH,
VIL or VOL, see Section 8.6, DC Electrical Characteristics on page 34). These signals are
described next.
3. Block/Sector Addresses
Table 2. Block/Sector Addresses of BY25D40
4. SPI Operation
4.1 Standard SPI Instructions
The BY25D40/20 features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip
Select (/CS), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are
supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge
of SCLK.
4.2 Dual SPI Instructions
The BY25D40/20 supports Dual SPI operation when using the “Dual Output Fast Read” (3BH)
instructions. These instructions allow data to be transferred to or from the device at two times the
rate of the standard SPI. When using the Dual SPI instruction the SI and SO pins become
bidirectional I/O pins: IO0 and IO1.
5. Operation Features
5.1 Supply Voltage
5.1.1 Operating Supply Voltage
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within
the specified [VCC(min), VCC(max)] range must be applied (see operating ranges of page 33). In
order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a
suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction and,
for a Write instruction, until the completion of the internal write cycle (tW).
5.1.2 Power-up Conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time,
the Chip Select (/CS) line is not allowed to float but should follow the VCC voltage, it is therefore
recommended to connect the /CS line to VCC via a suitable pull-up resistor.
In addition, the Chip Select (/CS) input offers a built-in safety feature, as the /CS input is edge
sensitive as well as level sensitive: after power-up, the device does not become selected until a
falling edge has first been detected on Chip Select (/CS). This ensures that Chip Select (/CS) must
have been High, prior to going Low to start the first operation.
5.1.3 Device Reset
In order to prevent inadvertent Write operations during power-up (continuous rise of VCC), a
power on reset (POR) circuit is included. At Power-up, the device does not respond to any
instruction until VCC has reached the power on reset threshold voltage (this threshold is lower
than the minimum VCC operating voltage defined in operating ranges of page 33).
When VCC has passed the POR threshold, the device is reset.
5.1.4 Power-down
At Power-down (continuous decrease in VCC), as soon as VCC drops from the normal operating
voltage to below the power on reset threshold voltage, the device stops responding to any
instruction sent to it. During Power-down, the device must be deselected (Chip Select (/CS) should
be allowed to follow the voltage applied on VCC) and in Standby Power mode (that is there should
be no internal Write cycle in progress).
5.2 Active Power and Standby Power Modes
When Chip Select (/CS) is Low, the device is selected, and in the Active Power mode. The device
consumes ICC.
When Chip Select (/CS) is High, the device is deselected. If a Write cycle is not currently in
progress, the device then goes in to the Standby Power mode, and the device consumption drops
to ICC1.
5.3 Status Register
The status and control bits of the Status Register are as follows:
WIP bit
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write
status register progress. When WIP bit sets to 1, means the device is busy in program/erase/write
status register progress, when WIP bit sets 0, means the device is not in program/erase/write
status register progress.
WEL bit
The Write Enable Latch bit indicates the status of the internal Write Enable Latch. When set to
1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and
no Write Status Register, Program or Erase instruction is accepted.
BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Program and Erase instructions. These bits are written with the Write
Status Register instruction. When the Block Protect (BP2, BP1, BP0) bits are set to 1, the relevant
memory area. Becomes protected against Page Program, Sector Erase and Block Erase
instructions. The Block Protect (BP2, BP1, BP0) bits can be written provided that the Hardware
Protected mode has not been set.
SRP bits
The Status Register Protect (SRP) bit operates in conjunction with the Write Protect (WP#)
signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal set the device
to the Hardware Protected mode. When the Status Register Protect (SRP) bit is set to 1, and Write
Protect (WP#) is driven Low. In this mode, the non-volatile bits of the Status Register (SRP, BP2,
BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is not
execution. The default value of SRP is 0.
5.3.1 Write Protect Features
1. Software Protection: The Block Protect (BP2, BP1, BP0) bits define the section of the memory
array that can be read but not change.
2. Hardware Protection: /WP going low to protected the BP0~BP2 bits and SRP bits.
3. Deep Power-Down: In Deep Power-Down Mode, all instructions are ignored except the
Release from deep Power-Down Mode instruction.
4. Write Enable: The Write Enable Latch (WEL) bit must be set prior to every Page Program,
Sector Erase, Block Erase, Chip Erase, Write Status Register and Erase/Program Security
Registers instruction.
