MX25L25645G

MXIC

3V, 256M-BIT [x 1/x 2/x 4] 

CMOS MXSMIO®

 (SERIAL MULTI I/O) 

FLASH MEMORY

Key Features

• Protocol Support - Single I/O, Dual I/O and Quad I/O

• Support DTR (Double Transfer Rate) Mode

• Support clock frequency up to 133MHz

1. FEATURES

GENERAL

• Supports Serial Peripheral Interface -- Mode 0 and 

Mode 3

• Single Power Supply Operation

 - 2.7 to 3.6 volt for read, erase, and program operations

• 268,435,456 x 1 bit structure

or 134,217,728 x 2 bits (two I/O mode) structure 

or 67,108,864 x 4 bits (four I/O mode) structure

• Protocol Support 

 - Single I/O, Dual I/O and Quad I/O

• Latch-up protected to 100mA from -1V to Vcc +1V

• Low Vcc write inhibit is from 1.5V to 2.5V

• Fast read for SPI mode

- Support clock frequency up to 133MHz for all 

protocols

- Support Fast Read, 2READ, DREAD, 4READ, 

QREAD instructions

- Support DTR (Double Transfer Rate) Mode

- Configurable dummy cycle number for fast read 

operation

• Quad Peripheral Interface (QPI) available

• Equal Sectors with 4K byte each, 

or Equal Blocks with 32K byte each 

or Equal Blocks with 64K byte each 

- Any Block can be erased individually

• Programming :

- 256byte page buffer 

- Quad Input/Output page program(4PP) to enhance

program performance

• Typical 100,000 erase/program cycles

• 20 years data retention

SOFTWARE FEATURES

• Input Data Format

 - 1-byte Command code

• Advanced Security Features

- Block lock protection

The BP0-BP3 and T/B status bits define the size of 

the area to be protected against program and erase 

instructions

- Individual sector protection function (Solid Protect)

3V 256M-BIT [x 1/x 2/x 4] CMOS MXSMIO®

 (SERIAL MULTI I/O) 

FLASH MEMORY

• Additional 4K bit security OTP

 - Features unique identifier 

 - Factory locked identifiable, and customer lockable

• Command Reset

• Program/Erase Suspend and Resume operation

• Electronic Identification

 - JEDEC 1-byte manufacturer ID and 2-byte device ID

- RES command for 1-byte Device ID

- REMS command for 1-byte manufacturer ID and 

1-byte device ID 

• Support Serial Flash Discoverable Parameters 

(SFDP) mode

HARDWARE FEATURES

• SCLK Input

 - Serial clock input

• SI/SIO0

 - Serial Data Input or Serial Data Input/Output for 

2 x I/O read mode and 4 x I/O read mode

• SO/SIO1

 - Serial Data Output or Serial Data Input/Output 

for 2 x I/O read mode and 4 x I/O read mode

• WP#/SIO2

 - Hardware Write Protection or Serial Data Input/

Output for 4 x I/O read mode

• RESET#/SIO3

 - Hardware Reset pin or Serial Data Input/Output 

for 4 x I/O read mode

• RESET#

 - Hardware Reset pin

• NC/SIO3

 - NC or Serial Data Input/Output for 4 x I/O read 

mode

• PACKAGE

- 16-pin SOP (300mil)

- 8-pins SOP (200mil)

- 8-land WSON (8x6mm, 6x5mm)

- 24-ball BGA (4x6 ball array) 

- 24-Ball BGA (5x5 ball array)

 - All devices are RoHS Compliant and Halogen-fre

2. GENERAL DESCRIPTION

MX25L25645G is 256Mb bits Serial NOR Flash memory, which is configured as 33,554,432 x 8 internally. When it 

is in two or four I/O mode, the structure becomes 134,217,728 bits x 2 or 67,108,864 bits x 4. 

MX25L25645G feature s a serial peripheral interface and software protocol allowing operation on a simple 3-wire 

bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a 

serial data output (SO). Serial access to the device is enabled by CS# input.

When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits 

input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# and RESET# pin (of the 8-pin 

packages) become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.

The MX25L25645G MXSMIO®

 (Serial Multi I/O) provides sequential read operation on the whole chip.

After program/erase command is issued, auto program/erase algorithms which program/erase and verify the 

specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 

bytes) basis, or word basis. Erase command is executed on 4K-byte sector, 32K-byte block, or 64K-byte block, or 

whole chip basis.

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read 

command can be issued to detect completion status of a program or erase operation via WIP bit.

Advanced security features enhance the protection and security functions, please see security features section for 

more details.

When the device is not in operation and CS# is high, it is put in standby mode.

The MX25L25645G utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 

100,000 program and erase cycles.

*Note: The pin of RESET#, RESET#/SIO3 or WP#/

SIO2 will remain internal pull up function while 

this pin is not physically connected in system 

configuration.

 However, the internal pull up function will be 

disabled if the system has physical connection 

to RESET#, RESET#/SIO3 or WP#/SIO2 pin.

6. DATA PROTECTION

During power transition, there may be some false system level signals which result in inadvertent erasure or 

programming. The device is designed to protect itself from these accidental write cycles.

The state machine will be reset as standby mode automatically during power up. In addition, the control register 

architecture of the device constrains that the memory contents can only be changed after specific command 

sequences have completed successfully. 

In the following, there are several features to protect the system from the accidental write cycles during VCC powerup and power-down or from system noise.

• Valid command length checking: The command length will be checked whether it is at byte base and completed 

on byte boundary.

• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before 

other command to change data. 

• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from 

writing all commands except Release from deep power down mode command (RDP) and Read Electronic 

Signature command (RES), and softreset command.

• Advanced Security Features: there are some protection and security features which protect content from 

inadvertent write and hostile access