TRICONEX 2381

TRICONEX 2381

TRICONEX 2381

TRICONEX 2381 Invensys main processor executes user written applications

The fault tolerance in Tricon is realized through the third mock examination redundancy (TMR) architecture. Tricon can provide error free and uninterrupted control in the event of hard faults or internal or external transient faults in components. Tricon adopts a completely triple architecture design, from the input module to the main processor and then to the output module. Each I/O module contains three independent branch circuits. Each pin on the input module reads process data and passes this information to their respective main processors. The three main processors communicate with each other using a proprietary high-speed bus system called TriBus. Every scan, the three main processors synchronize and communicate with their two neighbors through TriBus. Tricon votes on digital input data, compares output data, and sends copies of analog input data to each main processor. The main processor executes user written applications and sends the output generated by the application to the output module. In addition to voting on input data, TriBus also votes on output data. This is done on the output module as close to the field as possible to detect and compensate for any errors between the Tricon voting and the final output driven to the field.