CPU, buy T7200 2.0/4 m / 667 laptop CPU SL9SF original PGA official version support 945 platform on China Suppliers Mobile

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SL9SF specifications

General information

Type	CPU / Microprocessor
Family	Intel Core 2 Duo Mobile
Processor number ?	T7200
Part number	LF80537GF0414M BX80537T7200
Processor markings	LF80537 T7200 2.00/4M/667
Frequency (GHz) ?	2
Frequency in LFM mode (GHz)	1
Bus speed (MHz) ?	667
Clock multiplier ?	12
Package type	478-pin micro-FCPGA
Socket type	Socket M

Architecture / Microarchitecture / Other

CPUID	06F6h
Core stepping	B2
Manufacturing technology (micron)	0.065
Number of cores	2
L2 cache size (MB) ?	4
Features	EM64T technology ? Enhanced SpeedStep technology ? Execute disable bit ? Thermal Monitor 2 Virtualization technology
Core voltage (V) ?	1.075 - 1.25
Core voltage in LFM mode (V)	0.85 - 0.95
Case temperature (°C) ?	100
Thermal Design Power (Watt) ?	34

There are no notes on sSpec SL9SF

In addition to the SL9SF S-Spec, this processor was also manufactured with a few pre-production S-Spec numbers:

Stepping	S-Spec	LF80537GF0414M	BX80537T7200
B0	QLZX	+
B1	QOLP	+
B2	QTCI	+
B2	SL9SF	+	+
Unknown	QJEC	+

NOTE: Engineering and qualifications samples are marked with this color

View / search public CPUID submissions

Intel Core 2 Duo Mobile T7200 SL9SF

Part number:	LF80537GF0414M
Frequency:	1995 MHz

Comment:	on Toshiba Satellite J62 bios v4.0 replaced from CoreDuoT2300E
Submitted by:	nmspec

General information
Vendor:	GenuineIntel
Processor name (BIOS):	Intel(R) Core(TM)2 CPU T7200 @ 2.00GHz
Cores:	2
Logical processors:	2
Processor type:	Original OEM Processor
CPUID signature:	6F6
Family:	6 (06h)
Model:	15 (0Fh)
Stepping:	6 (06h)
TLB/Cache details:	3rd-level cache: 4-MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0Fh, Model 06h), 2nd-level cache: 4-MB, 16-way set associative, 64-byte line size 64-byte Prefetching Data TLB: 4-KB Pages, 4-way set associative, 256 entries Data TLB: 4-MB Pages, 4-way set associative, 32 entries Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries

Cache:	L1 data	L1 instruction	L2
Size:	2 x 32 KB	2 x 32 KB	4 MB
Associativity:	8-way set associative	8-way set associative	16-way set associative
Line size:	64 bytes	64 bytes	64 bytes
Comments:	Direct-mapped	Direct-mapped	Non-inclusive Direct-mapped Shared between all cores

Instruction set extensions		Additional instructions

MMX		CLFLUSH
SSE		CMOV
SSE2		CMPXCHG16B
SSE3		CMPXCHG8B
SSSE3		FXSAVE/FXRSTORE
		MONITOR/MWAIT
		SYSENTER/SYSEXIT

Major features		Other features
On-chip Floating Point Unit		36-bit page-size extensions
64-bit / Intel 64		64-bit debug store
Intel Virtualization		Advanced programmable interrupt controller
Enhanced SpeedStep		CPL qualified debug store
		Debug store
		Debugging extensions
		Digital Thermal Sensor capability
		LAHF/SAHF support in 64-bit mode
		Machine check architecture
		Machine check exception
		Memory-type range registers
		Model-specific registers
		Page attribute table
		Page global extension
		Page-size extensions (4MB pages)
		Pending break enable
		Perfmon and Debug capability
		Physical address extensions
		Self-snoop
		Thermal monitor
		Thermal monitor 2
		Thermal monitor and software controlled clock facilities
		Time stamp counter
		Virtual 8086-mode enhancements
		xTPR Update Control

Our CPUID database has 3 records for this microprocessor. See all submitted records.